This is a sample MIPS assembler code used to test EzMIPS functionality. All MIPS instructions and pseudo-instructions supported are tested for correct operation.
Launch EzMIPS, copy the following MIPS code and paste it into EzMIPS. Assemble, Run.
Launch EzMIPS, copy the following MIPS code and paste it into EzMIPS. Assemble, Run.
.text
main:
# .................. initialize some registers ............. #
li $2, 2
li $3, 0x3
li $4, 4
li $5, 5
li $6, 6
la $7, var_word01
# .......................................................... #
add $0, $5, $5
addi $10, $3, 0xfff4 # sign-extend(0xfff4) = 0xfffffff4)
addi $0, $3, 0xfff4
addiu $0, $3, 4
addu $0, $5, $5
and $0, $5, $3
andi $10, $3, -1 # -1 = 0xffff (ie NOT sign-extended)
andi $0, $2, 0xff
# beq $10, $2, exit
# bge $5, $2, exit
# bgez $5, exit
# bgezal $5, exit
# bgt $10, $2, exit
# bgtz $5, exit
# ble $10, $2, exit
# blez $5, exit
# blt $5, $8, exit
# bltz $5, exit
# bltzal $5, exit
# bne $10, $2, main
# break
div $4, $0
divu $3, $0
# j main
# jal exit
# jr $ra
# ......................... la ............................. #
la $0, var_word01 # actually testing ori instruction
la $0, main # actually testing ori instruction
la $10, var_word01
# .......................................................... #
lb $0, ($10)
lbu $0, 1($10)
li $0, 0x12345 # actually testing ori instruction
li $zero, 7 # actually testing ori instruction
li $0, 9 # actually testing ori instruction
lui $0, 0x100
# ....................... lw ............................... #
lw $0, ($7)
lw $0, var_byte01
# lw $12, var_half1 # Runtime exception at 0x00400084:
# fetch address not aligned on word
# boundary 0x10010002
lw $0, var_byte02
lw $0, var_word01
lw $0, var_half02
# ..................... mfhi, mflo ......................... #
# div $s, $t: $LO = $s/$t, $HI = $s%$t
div $5, $2 # 5\2 => $LO = 2 & $HI = 1
mfhi $0
mflo $0
# .......................................................... #
move $0, $2 # actually testing addu instruction
mul $0, $2, $5
mult $2, $5 # $LO = $s * $t
multu $2, $5 # $LO = $s * $t
nop
# .......................................................... #
nor $0, $2, $5
or $0, $2, $5
ori $10, $2, -1 # -1 = 0xffff (ie NOT sign-extended)
ori $0, $2, -1
sb $10, 0($7)
# .......................................................... #
# sll $10, $2, -2 # invalid 16-bit immediate value <-2>
sll $0, $2, 2
# li $3, 40
# sllv $14, $2, $3 # sllv: the number of bits to shift
# is given by the low order 5 bits
# of Rs (ie max 31)
sllv $0, $2, $3
# .......................................................... #
slt $0, $2, $5
slti $0, $2, 3
sltiu $0, $2, 3
sltu $0, $2, $5
# .......................................................... #
sra $0, $5, 1
# li $3, 33
# srav $14, $6, $3 # srav: the number of bits to shift
# is given by the low order 5 bits
# of Rs (ie max 31)
srav $0, $5, $2
# .......................................................... #
# srl $10, $2, -4 # invalid 16-bit immediate value <-4>
srl $0, $6, 1
# .......................................................... #
li $3, 33
srlv $14, $6, $3 # srlv: the number of bits to shift
# is given by the low order 5 bits
# of Rs (ie max 31)
srlv $0, $5, $2
# .......................................................... #
sub $0, $2, $5
subu $0, $5, $2
# li $2, 0xffffffff
# sub $12, $5, $2
# subu $13, $5, $2
# .......................................................... #
sw $10, 0($gp)
# sw $10, 1($gp) # Runtime exception at 0x00400100:
# sw $10, 2($gp) # store address not aligned on word
# sw $10, 3($gp) # boundary 0x1000800_
sw $10, var_word01
exit:
li $v0, 2
syscall # Warn. | line 169 | syscall <2> not supported
xor $0, $5, $3
xori $20, $s7, -1 # -1 = 0xffff (ie NOT sign-extended)
xori $0, $s7, 100
# ........................................................ #
.data
var_byte01: .byte 0xaa
var_half01: .half 0xbbcc
var_byte02: .byte 0xaa
var_word01: .word 0x12345678
var_half02: .half 0xddee
# ........................................................ #
Please let me know of any suggestions or bugs regarding the code above.
Regards,
Antonis
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