This is a sample MIPS assembler code to test the new instructions supported by EzMIPS v0.9.0.8. Although every care has been taken for the correct operation for all of them, I encourage you to test them thourougly and give me any feedback you feel appropriate. The new instructions are: jalr, lh, lhu, lwl, lwr, movn, movz, mthi, mtlo, sh, swl, swr, sync. The code is fully commented.
Launch EzMIPS, copy the following MIPS code and paste it into EzMIPS, the MIPS assembler editor & simulator. Assemble, Run.
# ---------------------------------------------------------------- #
# test program for the new instructions supported by EzMIPS v0.9.0.8 #Launch EzMIPS, copy the following MIPS code and paste it into EzMIPS, the MIPS assembler editor & simulator. Assemble, Run.
# ---------------------------------------------------------------- #
# ---------------------------------------------------------------- #
# New instructions:
# jalr, lh, lhu, lwl, lwr, movn, movz, mthi, mtlo, sh, swl, swr, sync #
.data
var_half0001: .half 0xf345
var_half0002: .half 0x0000
var_word0003: .word 0xdeadbeef
var_word0004: .word 0x11223344
var_word0005: .word 0x55667788
var_asciiz06: .asciiz "Hello "
var_asciiz07: .asciiz "there!\n"
# ---------------------------------------------------------------- #
.text
# ................................................................ #
main:
# initialize some registers for later use #
li $3, 100
li $5, 10
la $7, var_half0001
la $27, var_word0003
# ................................................................ #
la $t0, sub1 # load address of sub1()
jalr $t0 # $ra implied ie jalr $ra, $t0
# ie return address is kept in $ra
la $t0, sub2 # load address of sub2()
jalr $t1, $t0 # return address is kept in $t1
# ................................................................ #
#addiu $7, $7, 1
lh $5, 0($7) # check for align on halfword boundary; NICE
lhu $6, 0($7) # check for align on halfword boundary; NICE
# ................................................................ #
li $10, 0xffffffff
li $11, 0xffffffff
li $12, 0xffffffff
li $13, 0xffffffff
li $14, 0x00000000
li $15, 0x12121212
# ................................................................ #
lwl $10, 0($27)
lwl $11, 1($27)
lwl $12, 2($27)
lwl $13, 3($27)
lwl $14, 4($27)
lwl $15, 5($27)
# ................................................................ #
lwr $16, 0($27)
lwr $17, 1($27)
lwr $18, 2($27)
lwr $19, 3($27)
lwr $20, 4($27)
lwr $21, 5($27)
# ................................................................ #
movn $6, $5, $3
movz $7, $5, $3
# ................................................................ #
mthi $3
mtlo $5
# ................................................................ #
sh $21, 2($7)
#sh $22, 2($17)
#sh $1, 4($27)
#sh $2, 8($4)
# ................................................................ #
swl $22, 0($27)
swl $22, 1($27)
swl $22, 2($27)
swl $22, 3($27)
swl $13, 4($27)
swl $13, 5($27)
swl $13, 6($27)
swl $13, 7($27)
addi $27, $27, 8
swl $15, 0($27)
swl $15, 1($27)
swl $15, 2($27)
swl $15, 3($27)
# ............................................................... #
addi $27, $27, -8
swr $22, 0($27)
swr $22, 1($27)
swr $22, 2($27)
swr $22, 3($27)
swr $13, 4($27)
swr $13, 5($27)
swr $13, 6($27)
swr $13, 7($27)
addi $27, $27, 8
swr $15, 0($27)
swr $15, 1($27)
swr $15, 2($27)
swr $15, 3($27)
# ................................................................ #
#sync
# ................................................................ #
li $v0, 10 # return to OS
syscall
# ................................................................ #
sub1:
la $a0, var_asciiz06
li $v0, 4
syscall
jr $ra # return address is in $ra
# ................................................................ #
sub2:
la $a0, var_asciiz07
li $v0, 4
syscall
jr $t1 # return address is in $t1
# ................................................................ #
Please let me know of any suggestions or bugs regarding the code above.
Regards,
Antonis
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